Variable gain rf amplifier

ABSTRACT

A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of European patentapplication number 083095110.2, filed on Apr. 18, 2008, entitled“VARIABLE GAIN RF AMPLIFIER,” which is hereby incorporated by referenceto the maximum extent allowable by law.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a variable gain RF amplifier, and inparticular to a low noise variable gain RF amplifier.

2. Discussion of the Related Art

RF (radio frequency) devices such as radio tuners, mobile telephones,satellite receivers, TV tuners etc. are devices that receive an RFsignal. In such devices, input circuitry comprising a low noiseamplifier (LNA) is generally provided for amplifying the received RFsignal which is for example received via an antenna. The LNA shouldintroduce as little noise as possible to the signal. To avoid unwantedreflections, the input impedance of the LNA is usually matched to theimpedance of the antenna. Furthermore, the input circuitry generallyincludes a variable gain amplifier (VGA) coupled after the LNA, toadjust the amplitude of the RF signal to a range acceptable bydownstream circuitry that is to process the RF signal.

A drawback with such RF input circuitry is that in providing a low noiseamplifier coupled to a variable gain amplifier, the current consumptionis relatively high, and a relatively large amount of area is needed.Furthermore, due to the number of components that are present throughwhich the differential signal must pass, noise may be added to thesystem.

SUMMARY OF THE INVENTION

It is an aim of embodiments of the present invention to at leastpartially address one or more drawbacks in the prior art.

According to an aspect of the present invention, there is provided avariable gain amplifier comprising an input node; a variable currentsource comprising a control input coupled to the input node; first andsecond branches coupled in parallel between a first supply terminal andthe variable current source, the first and second branches defining adifferential pair arranged to be controlled by first and seconddifferential gain signals and comprising first and second outputterminals, one of the output terminals comprising an output node of thevariable gain amplifier; and a potential divider comprising a middlenode coupled to the first and second output terminals, wherein themiddle node is also coupled to the input node by a capacitor.

According to an embodiment of the present invention, the potentialdivider comprises a first resistor coupling the middle node to the firstoutput terminal and a second resistor coupling the middle node to thesecond output terminal.

According to another embodiment of the present invention, the first andsecond resistors have the same resistance value.

According to an embodiment of the present invention, the middle node iscoupled to the input node by the capacitor coupled in series with aresistor.

According to an embodiment of the present invention, the current sourcecomprises a transistor having a control terminal coupled to the inputnode, a first main current terminal coupled to a second supply terminaland a second main current terminal coupled to the first and secondbranches.

According to an embodiment of the present invention, the first branchcomprises a first transistor having a control terminal arranged toreceive the first differential gain signal, a first main currentterminal coupled to the current source and a second main currentterminal coupled to the first supply terminal; the second branchcomprises a second transistor having a control terminal arranged toreceive the second differential gain signal, a first main currentterminal coupled to the current source, and a second main currentterminal coupled to the first supply terminal; and the middle node ofthe potential divider is coupled to the second main current terminals ofthe first and second transistors.

According to an embodiment of the present invention, the variable gainamplifier further comprises a second input node; a second variablecurrent source comprising a control input coupled to the second inputnode; third and fourth branches coupled in parallel between a firstsupply terminal and the variable current source, the third and fourthbranches defining a differential pair arranged to be controlled by thefirst and second differential gain signals and comprising a second pairof output terminals, wherein the output node of the variable gainamplifier is a first output node of the variable gain amplifier andwherein one of the second pair of output terminals comprises a secondoutput node of the variable gain amplifier; and a second potentialdivider comprising a middle node coupled to the second pair of outputterminals, wherein the middle node is also coupled to the input node.

According to a further aspect of the present invention, there isprovided an RF device comprising an input for receiving an RF signal andthe above variable gain amplifier coupled to the input.

According to a further aspect of the present invention, there isprovided a mobile device comprising the above variable gain amplifier.

According to a further aspect of the present invention, there isprovided a satellite receiver comprising the above variable gainamplifier.

According to a further aspect of the present invention, there isprovided a system comprising receiving circuitry for receiving an RFsignal; an input node coupled to the receiving circuitry; a variablecurrent source comprising a control input coupled to the input node;first and second branches coupled in parallel between a first supplyterminal and the variable current source, the first and second branchesdefining a differential pair arranged to be controlled by first andsecond differential gain signals and comprising first and second outputterminals; one of the output terminals comprising an output node of thevariable gain amplifier; and a potential divider comprising a middlenode coupled to the first and second output terminals, wherein themiddle node is also coupled to the input node by a capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates input circuitry for receiving an RFsignal;

FIG. 2 schematically illustrates input circuitry according to anembodiment of the present invention comprising a low noise variable gainamplifier;

FIG. 3 is a circuit diagram of the low noise variable gain amplifier ofFIG. 2 according to one embodiment of the present invention;

FIG. 4 schematically illustrates input circuitry for receiving an RFsignal according to a further embodiment of the present inventioncomprising a low noise variable gain amplifier;

FIG. 5 is a circuit diagram of the low noise variable gain amplifier ofFIG. 4 according to an embodiment of the present invention; and

FIG. 6 schematically illustrates an RF device comprising a low noisevariable gain amplifier according to an embodiment of the presentinvention.

DETAILED DESCRIPTION

FIG. 1 illustrates input circuitry of an RF device for receiving an RFsignal via an antenna 100. Antenna 100 is coupled to a balun 102, whichconverts an unbalanced signal into a balanced signal, and in particularthe signal from the antenna into a differential signal comprisingcomplementary parts. The differential signal is provided on two lines103 and 104 to a low noise amplifier (LNA) 106, which amplifies thedifferential signal. The differential output of LNA 106 is coupled to avariable gain amplifier (VGA) 108, which amplifies the differentialsignal by a required amount such that the components of the differentialoutput signal RF_(OUTP) and RF_(OUTN) have the required amplitudes. VGA108 is controlled by a feedback loop.

Such an arrangement comprising separate circuitry for providing an LNAand a VGA has drawbacks, as discussed in the background section above.In particular, the LNA is likely to comprise at least one transistor foramplifying each part of the differential RF signal, while the VGA islikely to include a number of transistors for applying a variable gainto each part of the differential RF signal. Each stage adds currentconsumption to the device as well as area, and may also add noise to theRF signal.

FIG. 2 illustrates input circuitry of an RF device comprising an antenna200 and a low noise variable gain amplifier (from here onwards LNVGA)202 having an input coupled to the antenna 200, for example via ahigh-pass filter, for receiving an RF input signal RF_(IN), and anoutput RF_(OUT), which in this example is a single-ended output. LNVGA202 combines the functions of LNA 106 and VGA 108 of FIG. 1, but foramplifying a single-ended RF signal. By combining these blocks into oneblock, the number of components can be reduced, and consequently currentconsumption can be reduced, area of the device can also be reduced, andless noise is introduced into the RF signal.

FIG. 3 is a circuit diagram illustrating the LNVGA 202 of FIG. 2 in moredetail.

LNVGA 202 comprises an input node 302 coupled to the base terminal of abipolar transistor 304, which has its emitter terminal coupled to aground reference via a resistor 306, and its collector terminal coupledto a node 307. Transistor 307 provides a variable current source,controlled by an input signal applied to node 302.

Node 307 is coupled to branches 308, 309 which define a differentialpair. In particular, branch 308 comprises a bipolar transistor 310having an emitter terminal connected to node 307, while branch 309comprises a bipolar transistor 311 having an emitter terminal coupled tonode 307. The base terminals of transistors 310, 311 are coupled tonodes 312 and 313 respectively. Nodes 312 and 313 receive differentialgain control signals generated by a feedback path from the output of theLNVGA 202. For example, node 312 receives a gain signal V_(gainP) whilenode 313 receives a gain signal V_(gain)N, signals V_(gainP) andV_(gainN) being differential signals generated based on a feedbacksignal from the output of LNVGA 202.

By way of example, gain signals V_(gainP) and V_(gainN) are output by asingle to differential attenuator with output common mode regulation andlow output impedance. The single ended input to the attenuator is, forexample, provided by a power sensor that senses the LNVGA output power.

The collector terminal of bipolar transistor 310 is coupled to a node314, which is in turn coupled to the supply voltage level V_(DD) via aresistor 316. The collector terminal of bipolar transistor 311 iscoupled to a node 318, which is in turn coupled to the supply voltagelevel V_(DD) via a resistor 320. Nodes 314 and 318 provide outputs ofthe differential pair provided by transistors 310 and 311. Furthermore,node 314 provides the output node of the LNVGA 202, providing the RFoutput signal RF_(OUT).

Nodes 314 and 318 are coupled via respective resistors 322 and 324 ofequal resistance, to a node 326, which is in turn coupled to the inputnode 302 via a capacitor 328 and resistor 330 coupled in series. Node326 is a middle node of a potential divider provided by resistors 322and 324 between nodes 314 and 318, and thus has a voltage level betweenthe voltage levels of nodes 314 and 318, for example a voltage levelhalfway between these voltage levels.

In operation, node 302 is AC coupled to receive an RF input signalRF_(IN), which in this example is the signal received via antenna 200 ofFIG. 2, although in alternative embodiments the input signal could bereceived via a different communications path, such as a transmissioncable. This RF signal is amplified by bipolar transistor 304, based onthe values of resistors 306, 316, 320, 322, 324 and 330, and by the gainassociated with bipolar transistors 310 and 311. In particular, assumingthat coupling capacitors are high enough, transistors are ideal (veryhigh gm, β and Early voltage and no parasitic capacitances) resistor 306has a resistance R₁, resistors 316 and 320 have the same resistance R₂,resistors 322 and 324 the same resistance R₃, and resistor 330 aresistance R₄, the gain G defined as RF_(OUT)/RF_(IN) can be expressedas:

-   -   G=R₂((R₁(R₂+R₃)-gR₃(R₂+R₃+2R₄)—R₄R₂))/R₁(R₂+R₃)(R₂+R₃+2R₄)˜(1)

“g” for example has a value between 0 and 1 and is a function ofVgainP-VgainN. Assuming R3 is infinity, VoutN/VinP=−gR2/R1. When g isequal to 0, all current passes through transistor 311, whereas when g isequal to 1, all current passes through transistor 310.

Thus, the values of R1 to R4 can be chosen to provide a desired fixedgain of the circuit. As an example, the resistance values could be asfollows: R₁=13 Ohms; R₂=200 Ohms; R₃=140 Ohms; and R₄=98 Ohms. Thesevalues result in a gain of the circuit of −1.281-6.335 g.

One of the aims of the circuitry of the variable gain amplifier 202 ofFIG. 3 is to provide a circuit having an input impedance matched to theimpedance of the input line whatever the gain selection (g value), toavoid reflections. The input line has an impedance associated with theantenna. To match this impedance, which is for example approximately 30Ohms, a resistor 330 is provided, having a resistance R4, coupledbetween the input 302 and a node 326. Node 326 is at a mid voltagebetween nodes 314 and 318, achieved by connecting node 326 to node 314and 318 respectively by resistors 322 and 324, which have equalresistances. Assuming the values R₁ to R₄ of the resistors in thecircuit of FIG. 3, the input impedance Z_(IN) can be expressed asfollows:

-   -   Z_(IN)=R₁(R₂+R₃+2R₄)/(2R₁+R₂)

The numerical examples provided above thus provide an input impedance ofapproximately 31 Ohms.

Capacitor 328 provided between the input node 302 and node 326 preventsa DC connection between these nodes and is designed to provide lowimpedance at the operating frequency of the amplifier which is forexample in the GHz range. Capacitor 328, for example, has a capacitanceof approximately 20 pF, which is suitable for input frequencies of theinput signal in a range of approximately 0.95 GHz to 2.15 GHz.

FIG. 4 illustrates RF input circuitry comprising an antenna 400 coupledto a balun 402, which generates a differential signal comprising a pairof complementary signals on lines 403, 404 based on the signal providedby the antenna 400. Lines 403, 404 are connected to an LNVGA 406. Inthis embodiment, the differential output of the LNVGA 406 on lines 407,408 is provided to an output buffer 410, which is for example apush-pull buffer. The role of this buffer is to present a very lowoutput impedance to cope with the input of the next block, which couldbe a matrix or mixer, for example.

FIG. 5 illustrates the low noise variable gain amplifier 406 of FIG. 4in more detail.

The left-hand side of circuitry 406 delimited by dashed box 501 isidentical to the circuitry in FIG. 3, and has been labeled with the samereference numerals except that each numeral starts with a “5” ratherthan a “3”. In particular, features labeled 502 to 530 correspond tofeatures labeled 302 to 330 in FIG. 3, and these features will not bedescribed again in detail.

Whereas resistor 306 in FIG. 3 is coupled to ground, resistor 506 inFIG. 5 is coupled to a grounded resistor 531, although in someembodiments resistor 506 could be coupled directly to ground.

The right hand side of circuitry 406 is an image of the left hand side,as will now be explained. The right hand side comprises an input node532, coupled to the base terminal of a bipolar transistor 534, which hasits emitter coupled to a resistor 536 which is in turn coupled togrounded resistor 531, and its collector terminal coupled to a node 537.As with transistor 504, transistor 534 provides a variable currentsource, controlled by the input signal provided at input node 532.

Node 537 is coupled to branches 538 and 539 that define a differentialpair. Branch 538 comprises a bipolar transistor 540 having its emitterterminal connected to node 537, while branch 539 comprises a bipolartransistor 541 having its emitter terminal connected to node 537. Thebase terminal of bipolar transistor 541 is coupled to node 513 and inthis embodiment, gain signal V_(gainN) is, for example, applied at thisnode. The base terminal of bipolar transistor 540 is coupled to node512, which, as descried above, receives a feedback gain signalV_(gainP). Again, V_(gainN) and V_(gainP) are differential gain signals.

The collector terminal of bipolar transistor 540 is coupled to a node544, which is in turn coupled to the supply voltage V_(DD) via aresistor 546. The collector of bipolar transistor 541 is coupled to anode 548, which is in turn coupled to the supply voltage V_(DD) via aresistor 550. Nodes 544 and 548 provide outputs of the differential pairprovided by transistors 540 and 541. Furthermore, node 544 provides oneof the differential output nodes of the LNVGA 406, providing the RFoutput signal RF_(OUTP). The other differential output RF_(OUTN) isprovided by node 514 of the left hand side 501.

Nodes 544 and 548 are coupled to a node 556 via resistors 552 and 554respectively. Node 556 is coupled to the input node 532 via a capacitor558 and a resistor 560 coupled in series. Thus, node 556 is a middlenode of a potential divider provided by resistors 552 and 554, and thushas a voltage level between the voltage levels of nodes 548 and 544,halfway between these voltage levels if resistors 552 and 554 have equalresistance.

The operation of the circuit in FIG. 5 is similar to that of FIG. 3,except that now there are differential input and output signals. Theinput signals RF_(INP) and RF_(INN) at nodes 502 and 532 respectivelycan be provided by an antenna, or different communications path, via abalun to generate the different components. The gain signals V_(gainN)and V_(gainP) provided at node 513 and to nodes 512 are based on afeedback signal, provided to circuitry that generates these differentialgain signals. The gain RF_(OUTP)/RF_(INN) or RF_(OUTN)/RF_(INP) of theLNVGA 406 can be determined by formula (1) above, while the inputimpedance of each side of LNVGA 406 can be determined by formula (2)above, assuming that resistors 506 and 536 have resistance R1, resistors516, 520, 546 and 550 have resistance R2, resistors 522, 524, 552 and554 have resistance R3 and resistors 530 and 560 have resistance R4. Inthis embodiment, to match an impedance of 75 Ohms differential of theantenna, the input impedance of each side of LNVGA 406 is for exampleequal to 37.5 Ohms.

FIG. 6 illustrates a device 600, which is an RF device arranged toreceive an RF signal. The circuitry comprises an antenna 602, which, asillustrated, may be incorporated in device 600, or, as shown by thedashed line, it could be an external component coupled to device 600.

Antenna 602 is coupled to RF input circuitry 604, which comprises a lownoise variable gain amplifier as described above and generates adifferential signal having complementary components provided on lines605 and 606. In this embodiment, the differential output of RF inputcircuitry 604 on lines 605 and 606 is coupled to a buffer 608, which inturn outputs a differential signal on lines 609, 610 to circuitry 612,which processes the received RF signal. Circuitry 612, for example,comprises an RF mixer and may also include a processor that converts theRF signal from the RF mixer into a digital signal or performs otherprocessing on the signal, before providing an output on line 614, whichcould be coupled to an internal or external display (not shown in FIG.6) or other output device.

An advantage of the embodiments of an LNVGA described herein is that incombining a low noise amplifier having input impedance matching with avariable gain amplifier in a single device, the number of componentsthat the input RF signal passes through can be very low, and the currentconsumption and area of the device can be, for example, halved. Inparticular, in the above embodiments, a gain transistor, in other wordsa variable current source, and a differential pair are provided betweeneach input and output node. A further advantage of the embodimentsdescribed above is that by coupling the input node to a mid pointbetween differential outputs of the differential pair, such that thecurrent flowing from the input node to this mid point does not depend onthe gain g of the differential pair, a fixed input impedance can beprovided at the same time as the variable gain functionality.

A further advantage of embodiments described herein is that by providingresistor 330, 530 and 560 coupling the input nodes to the potentialdividers, the correlation between input impedance matching and gainvariation range when g=0.5 can be reduced.

While a number of particular embodiments have been described, it will beapparent to those skilled in the art that various modifications can beapplied.

For example, while in the described embodiments the transistors aredescribed as being bipolar transistors such as bipolar junctiontransistors (BJT), in alternative embodiments other types of transistorscould be used, and in particular one or more of the transistors could bereplaced by MOS (metal oxide semiconductor) transistors. It will also beapparent to those skilled in the art that while all of the transistorsillustrated in the various embodiments are NPN bipolar transistors, itwould be possible to replace one or more of these by PNP bipolartransistors. However, advantageously, NPN transistors can generallyprovide a higher gain and faster response than PNP transistors.

Furthermore, it will be apparent that it would be possible to invert thecircuits of FIGS. 3 or 5, such that VDD and ground are inversed. Theground voltage level need not be at zero volts, while the supply voltagelevel could be positive or negative.

While the described embodiments include resistors 330, 530 and 560coupled to the input nodes, it will be apparent that these could beremoved. Furthermore, the potential divider provided by resistors 322and 324 in FIG. 3, and potential dividers provided by resistors 522, 524and 554, 552 in FIG. 5 could instead be provided by current sources.

It will also be apparent to those skilled in the art that while theembodiments of the LNVGA have been described as receiving an RF signalreceived from an antenna, the RF signal could be received fromelsewhere, including other circuitry, or other communications paths.

Additionally, while the use of an output buffer has been described inrelation to FIGS. 4 and 6, the embodiment of FIG. 2 could also includean output buffer positioned after the LNVGA.

Having thus described at least one illustrative embodiment of theinvention, various alterations, modifications, and improvements willreadily occur to those skilled in the art. Such alterations,modifications, and improvements are intended to be within the spirit andscope of the invention. Accordingly, the foregoing description is by wayof example only and is not intended as limiting. The invention islimited only as defined in the following claims and the equivalentsthereto.

1. A variable gain amplifier comprising: an input node; a variablecurrent source having a control input coupled to said input node; firstand second branches coupled in parallel between a first supply terminaland said variable current source, said first and second branchesdefining a differential pair arranged to be controlled by first andsecond differential gain signals and comprising first and second outputterminals, one of said output terminals comprising an output node ofsaid variable gain amplifier; and a potential divider having a middlenode coupled to said first and second output terminals, wherein saidmiddle node is also coupled to said input node by a capacitor.
 2. Thevariable gain amplifier of claim 1, wherein said potential dividercomprises a first resistor coupling said middle node to said firstoutput terminal and a second resistor coupling said middle node to saidsecond output terminal.
 3. The variable gain amplifier of claim 2,wherein said first and second resistors have the same resistance value.4. The variable gain amplifier of claim 1, wherein said middle node iscoupled to said input node by said capacitor coupled in series with aresistor.
 5. The variable gain amplifier of claim 1, wherein saidcurrent source comprises a transistor having a control terminal coupledto said input node, a first main current terminal coupled to a secondsupply terminal and a second main current terminal coupled to said firstand second branches.
 6. The variable gain amplifier of claim 1, wherein:said first branch comprises a first transistor having a control terminalarranged to receive said first differential gain signal, a first maincurrent terminal coupled to said current source and a second maincurrent terminal coupled to said first supply terminal; said secondbranch comprises a second transistor having a control terminal arrangedto receive said second differential gain signal, a first main currentterminal coupled to said current source, and a second main currentterminal coupled to said first supply terminal; and said middle node ofsaid potential divider is coupled to said second main current terminalsof said first and second transistors.
 7. The variable gain amplifier ofclaim 1, further comprising: a second input node; a second variablecurrent source having a control input coupled to said second input node;third and fourth branches coupled in parallel between a first supplyterminal and said variable current source, said third and fourthbranches defining a differential pair arranged to be controlled by saidfirst and second differential gain signals and comprising a second pairof output terminals, wherein said output node of said variable gainamplifier is a first output node of said variable gain amplifier andwherein one of said second pair of output terminals comprises a secondoutput node of said variable gain amplifier; and a second potentialdivider having a middle node coupled to said second pair of outputterminals, wherein said middle node is also coupled to said input node.8. An RF device comprising: an input for receiving an RF signal; thevariable gain amplifier of claim 1 coupled to said input.
 9. A mobiledevice comprising the variable gain amplifier of claim
 1. 10. Asatellite receiver comprising the variable gain amplifier of claim 1.11. A system comprising: receiving circuitry for receiving an RF signal;an input node coupled to said receiving circuitry; a variable currentsource having a control input coupled to said input node; first andsecond branches coupled in parallel between a first supply terminal andsaid variable current source, said first and second branches defining adifferential pair arranged to be controlled by first and seconddifferential gain signals and comprising first and second outputterminals; one of said output terminals comprising an output node ofsaid variable gain amplifier; and a potential divider having a middlenode coupled to said first and second output terminals, wherein saidmiddle node is also coupled to said input node by a capacitor